PLL3SRC=B_0x0, PLL3REN=B_0x0, PLL3PEN=B_0x0, PLL3QEN=B_0x0, PLL3M=B_0x0
RCC PLL3 configuration register
| PLL3SRC | PLL3 entry clock source This bitfield is set and cleared by software to select PLL3 clock source. It can be written only when the PLL3 is disabled. To save power, when no PLL3 is used, this bitfield value must be�zero. 0 (B_0x0): No clock sent to PLL3 1 (B_0x1): MSIS clock selected as PLL3 clock entry 2 (B_0x2): HSI16 clock selected as PLL3 clock entry 3 (B_0x3): HSE clock selected as PLL3 clock entry |
| PLL3RGE | PLL3 input frequency range This bit is set and reset by software to select the proper reference frequency range used for�PLL3. It must be written before enabling the PLL3. 00-01-10: PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL3 input (ref3_ck) clock range frequency between 8 and 16 MHz |
| PLL3FRACEN | PLL3 fractional latch enable This bit is set and reset by software to latch the content of PLL3FRACN in the ΣΔ modulator. In order to latch the PLL3FRACN value into the ΣΔ modulator, PLL3FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL3FRACN into the modulator (see PLL initialization phase for details). |
| PLL3M | Prescaler for PLL3 This bitfield is set and cleared by software to configure the prescaler of the PLL3. The VCO3 input frequency is PLL3 input clock frequency/PLL3M. This bitfield can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). … 0 (B_0x0): division by 1 (bypass) 1 (B_0x1): division by 2 2 (B_0x2): division by 3 15 (B_0xF): division by 16 |
| PLL3PEN | PLL3 DIVP divider output enable This bit is set and reset by software to enable the pll3_p_ck output of the PLL3. To save power, PLL3PEN and PLL3P bits must be set to 0 when pll3_p_ck is not used. 0 (B_0x0): pll3_p_ck output disabled 1 (B_0x1): pll3_p_ck output enabled |
| PLL3QEN | PLL3 DIVQ divider output enable This bit is set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, PLL3QEN and PLL3Q bits must be set to 0 when pll3_q_ck is not used. 0 (B_0x0): pll3_q_ck output disabled 1 (B_0x1): pll3_q_ck output enabled |
| PLL3REN | PLL3 DIVR divider output enable This bit is set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, PLL3REN and PLL3R bits must be set to 0 when pll3_r_ck is not used. 0 (B_0x0): pll3_r_ck output disabled 1 (B_0x1): pll3_r_ck output enabled |