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STMicroelectronics /STM32U5A5 /CRS /ISR

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Interpret as ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYNCOKF)SYNCOKF 0 (SYNCWARNF)SYNCWARNF 0 (ERRF)ERRF 0 (ESYNCF)ESYNCF 0 (SYNCERR)SYNCERR 0 (SYNCMISS)SYNCMISS 0 (TRIMOVF)TRIMOVF 0 (FEDIR)FEDIR 0FECAP

Description

interrupt and status register

Fields

SYNCOKF

SYNC event OK flag
SYNCWARNF

SYNC warning flag
ERRF

Error flag
ESYNCF

Expected SYNC flag
SYNCERR

SYNC error
SYNCMISS

SYNC missed
TRIMOVF

Trimming overflow or underflow
FEDIR

Frequency error direction
FECAP

Frequency error capture

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data