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STMicroelectronics /STM32U5A5 /FDCAN1_RAM /FDCAN_DBTP

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Interpret as FDCAN_DBTP

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DSJW0DTSEG20DTSEG10DBRP0 (TDC)TDC

Description

FDCAN Data Bit Timing and Prescaler Register

Fields

DSJW

Synchronization Jump Width
DTSEG2

Data time segment after sample point
DTSEG1

Data time segment after sample point
DBRP

Data BIt Rate Prescaler
TDC

Transceiver Delay Compensation

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data