Regviz

STMicroelectronics /STM32U5A5 /FMC /BWTR1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as BWTR1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32U599/FMC/BWTR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADDSET0ADDHLD0DATAST0BUSTURN0ACCMOD 0DATAHLD

Description

SRAM/NOR-Flash write timing registers 1

Fields

ADDSET

Address setup phase duration
ADDHLD

Address-hold phase duration
DATAST

Data-phase duration
BUSTURN

Bus turnaround phase duration
ACCMOD

Access mode
DATAHLD

Data hold phase duration

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data