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STMicroelectronics /STM32U5A5 /GTZC2_TZIC /IER1

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Interpret as IER1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI3IE)SPI3IE 0 (LPUART1IE)LPUART1IE 0 (I2C3IE)I2C3IE 0 (LPTIM1IE)LPTIM1IE 0 (LPTIM3IE)LPTIM3IE 0 (LPTIM4IE)LPTIM4IE 0 (OPAMPIE)OPAMPIE 0 (COMPIE)COMPIE 0 (ADC2IE)ADC2IE 0 (VREFBUFIE)VREFBUFIE 0 (DAC1IE)DAC1IE 0 (ADF1IE)ADF1IE

Description

TZIC interrupt enable register 1

Fields

SPI3IE

illegal access interrupt enable for SPI3
LPUART1IE

illegal access interrupt enable for LPUART1
I2C3IE

illegal access interrupt enable for I2C3
LPTIM1IE

illegal access interrupt enable for LPTIM1
LPTIM3IE

illegal access interrupt enable for LPTIM3
LPTIM4IE

illegal access interrupt enable for LPTIM4
OPAMPIE

illegal access interrupt enable for OPAMP
COMPIE

illegal access interrupt enable for COMP
ADC2IE

illegal access interrupt enable for ADC2
VREFBUFIE

illegal access interrupt enable for VREFBUF
DAC1IE

illegal access interrupt enable for DAC1
ADF1IE

illegal access interrupt enable for ADF1

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data