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STMicroelectronics /STM32U5A5 /LPTIM4 /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENABLE)ENABLE 0 (SNGSTRT)SNGSTRT 0 (CNTSTRT)CNTSTRT 0 (COUNTRST)COUNTRST 0 (RSTARE)RSTARE

Description

Control Register

Fields

ENABLE

LPTIM Enable
SNGSTRT

LPTIM start in single mode
CNTSTRT

Timer start in continuous mode
COUNTRST

Counter reset
RSTARE

Reset after read enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data