STMicroelectronics /STM32U5A5 /OTG_HS /DIEPCTL0

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Interpret as DIEPCTL0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MPSIZ 0 (USBAEP)USBAEP 0 (NAKSTS)NAKSTS 0EPTYP 0 (STALL)STALL 0TXFNUM0 (CNAK)CNAK 0 (SNAK)SNAK 0 (EPDIS)EPDIS 0 (EPENA)EPENA

Description

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Fields

MPSIZ

MPSIZ

USBAEP

USBAEP

NAKSTS

NAKSTS

EPTYP

EPTYP

STALL

STALL

TXFNUM

TXFNUM

CNAK

CNAK

SNAK

SNAK

EPDIS

EPDIS

EPENA

EPENA

Links

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