STMicroelectronics /STM32U5A5 /PWR /PWR_SR

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Interpret as PWR_SR

STOPF=B_0x0, SBF=B_0x0

Description

PWR status register

Fields

CSSF	Clear Stop and Standby flags This bit is protected against non-secure access when LPMSEC = 1 in PWR_SECCFGR. This bit is protected against unprivileged access when LPMSEC = 1 and SPRIV = 1 in PWR_PRIVCFGR, or when LPMSEC = 0 and NSPRIV = 1. Writing 1 to this bit clears the STOPF and SBF flags.
STOPF	Stop flag This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit. 0 (B_0x0): The device did not enter any Stop mode. 1 (B_0x1): The device entered a Stop mode.
SBF	Standby flag This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset. 0 (B_0x0): The device did not enter Standby mode. 1 (B_0x1): The device entered Standby mode.

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