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STMicroelectronics /STM32U5A5 /PWR /PWR_WUSCR

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Interpret as PWR_WUSCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CWUF1)CWUF1 0 (CWUF2)CWUF2 0 (CWUF3)CWUF3 0 (CWUF4)CWUF4 0 (CWUF5)CWUF5 0 (CWUF6)CWUF6 0 (CWUF7)CWUF7 0 (CWUF8)CWUF8

Description

PWR wakeup status clear register

Fields

CWUF1

Wakeup flag 1 Writing 1 to this bit clears the WUF1 flag in PWR_WUSR.
CWUF2

Wakeup flag 2 Writing 1 to this bit clears the WUF2 flag in PWR_WUSR.
CWUF3

Wakeup flag 3 Writing 1 to this bit clears the WUF3 flag in PWR_WUSR.
CWUF4

Wakeup flag 4 Writing 1 to this bit clears the WUF4 flag in PWR_WUSR.
CWUF5

Wakeup flag 5 Writing 1 to this bit clears the WUF5 flag in PWR_WUSR.
CWUF6

Wakeup flag 6 Writing 1 to this bit clears the WUF6 flag in PWR_WUSR.
CWUF7

Wakeup flag 7 Writing 1 to this bit clears the WUF7 flag in PWR_WUSR.
CWUF8

Wakeup flag 8 Writing 1 to this bit clears the WUF8 flag in PWR_WUSR.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data