DCMI_PSSIEN=B_0x0, ADC12EN=B_0x0, RNGEN=B_0x0, OTFDEC2EN=B_0x0, GPIOBEN=B_0x0, GPIOJEN=B_0x0, OTGHSPHYEN=B_0x0, SDMMC2EN=B_0x0, GPIOAEN=B_0x0, GPIOIEN=B_0x0, SAESEN=B_0x0, GPIODEN=B_0x0, OTFDEC1EN=B_0x0, PKAEN=B_0x0, HASHEN=B_0x0, OCTOSPIMEN=B_0x0, SRAM3EN=B_0x0, SRAM2EN=B_0x0, AESEN=B_0x0, OTGEN=B_0x0, SDMMC1EN=B_0x0, GPIOHEN=B_0x0, GPIOGEN=B_0x0, GPIOFEN=B_0x0, GPIOEEN=B_0x0, GPIOCEN=B_0x0
RCC AHB2 peripheral clock enable register 1
| GPIOAEN | I/O port A clock enable This bit is set and cleared by software. 0 (B_0x0): I/O port A clock disabled 1 (B_0x1): I/O port A clock enabled |
| GPIOBEN | I/O port B clock enable This bit is set and cleared by software. 0 (B_0x0): I/O port B clock disabled 1 (B_0x1): I/O port B clock enabled |
| GPIOCEN | I/O port C clock enable This bit is set and cleared by software. 0 (B_0x0): I/O port C clock disabled 1 (B_0x1): I/O port C clock enabled |
| GPIODEN | I/O port D clock enable This bit is set and cleared by software. 0 (B_0x0): I/O port D clock disabled 1 (B_0x1): I/O port D clock enabled |
| GPIOEEN | I/O port E clock enable This bit is set and cleared by software. 0 (B_0x0): I/O port E clock disabled 1 (B_0x1): I/O port E clock enabled |
| GPIOFEN | I/O port F clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): I/O port F clock disabled 1 (B_0x1): I/O port F clock enabled |
| GPIOGEN | I/O port G clock enable This bit is set and cleared by software. 0 (B_0x0): I/O port G clock disabled 1 (B_0x1): I/O port G clock enabled |
| GPIOHEN | I/O port H clock enable This bit is set and cleared by software. 0 (B_0x0): I/O port H clock disabled 1 (B_0x1): I/O port H clock enabled |
| GPIOIEN | I/O port I clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): I/O port I clock disabled 1 (B_0x1): I/O port I clock enabled |
| GPIOJEN | I/O port J clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): I/O port J clock disabled 1 (B_0x1): I/O port J clock enabled |
| ADC12EN | ADC1 and ADC2 clock enable This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx. 0 (B_0x0): ADC1 and ADC2 clock disabled 1 (B_0x1): ADC1 and ADC2 clock enabled |
| DCMI_PSSIEN | DCMI and PSSI clock enable This bit is set and cleared by software. 0 (B_0x0): DCMI and PSSI clock disabled 1 (B_0x1): DCMI and PSSI clock enabled |
| OTGEN | OTG_FS or OTG_HS clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): OTG_FS or OTG_HS clock disabled 1 (B_0x1): OTG_FS or OTG_HS clock enabled |
| OTGHSPHYEN | OTG_HS PHY clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): OTG_HS PHY clock disabled 1 (B_0x1): OTG_HS PHY clock enabled |
| AESEN | AES clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): AES clock disabled 1 (B_0x1): AES clock enabled |
| HASHEN | HASH clock enable This bit is set and cleared by software 0 (B_0x0): HASH clock disabled 1 (B_0x1): HASH clock enabled |
| RNGEN | RNG clock enable This bit is set and cleared by software. 0 (B_0x0): RNG clock disabled 1 (B_0x1): RNG clock enabled |
| PKAEN | PKA clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): PKA clock disabled 1 (B_0x1): PKA clock enabled |
| SAESEN | SAES clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): SAES clock disabled 1 (B_0x1): SAES clock enabled |
| OCTOSPIMEN | OCTOSPIM clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): OCTOSPIM clock disabled 1 (B_0x1): OCTOSPIM clock enabled |
| OTFDEC1EN | OTFDEC1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): OTFDEC1 clock disabled 1 (B_0x1): OTFDEC1 clock enabled |
| OTFDEC2EN | OTFDEC2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): OTFDEC2 clock disabled 1 (B_0x1): OTFDEC2 clock enabled |
| SDMMC1EN | SDMMC1 clock enable This bit is set and cleared by software. 0 (B_0x0): SDMMC1 clock disabled 1 (B_0x1): SDMMC1 clock enabled |
| SDMMC2EN | SDMMC2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): SDMMC2 clock disabled 1 (B_0x1): SDMMC2 clock enabled |
| SRAM2EN | SRAM2 clock enable This bit is set and reset by software. 0 (B_0x0): SRAM2 clock disabled 1 (B_0x1): SRAM2 clock enabled |
| SRAM3EN | SRAM3 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): SRAM3 clock disabled 1 (B_0x1): SRAM3 clock enabled |