RegViz: Visualize RCC_AHB2SMENR2 Bitfield

STMicroelectronics /STM32U5A5 /RCC /RCC_AHB2SMENR2

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Interpret as RCC_AHB2SMENR2

SRAM5SMEN=B_0x0, FSMCSMEN=B_0x0, OCTOSPI1SMEN=B_0x0, HSPI1SMEN=B_0x0, OCTOSPI2SMEN=B_0x0, SRAM6SMEN=B_0x0

Description

RCC AHB2 peripheral clock enable in Sleep and Stop modes register 2

Fields

FSMCSMEN	FSMC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): FSMC clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): FSMC clocks enabled by the clock gating during Sleep and Stop modes
OCTOSPI1SMEN	OCTOSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): OCTOSPI1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): OCTOSPI1 clocks enabled by the clock gating during Sleep and Stop modes
OCTOSPI2SMEN	OCTOSPI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): OCTOSPI2 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): OCTOSPI2 clocks enabled by the clock gating during Sleep and Stop modes
HSPI1SMEN	HSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): HSPI1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): HSP1I clocks enabled by the clock gating during Sleep and Stop modes
SRAM6SMEN	SRAM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): SRAM6 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SRAM6 clocks enabled by the clock gating during Sleep and Stop modes
SRAM5SMEN	SRAM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): SRAM5 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SRAM5 clocks enabled by the clock gating during Sleep and Stop modes

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