USART1SMEN=B_0x0, DSISMEN=B_0x0, LTDCSMEN=B_0x0, TIM16SMEN=B_0x0, SPI1SMEN=B_0x0, SAI2SMEN=B_0x0, GFXTIMSMEN=B_0x0, TIM8SMEN=B_0x0, TIM1SMEN=B_0x0, USBSMEN=B_0x0, SAI1SMEN=B_0x0, TIM17SMEN=B_0x0, TIM15SMEN=B_0x0
RCC APB2 peripheral clocks enable in Sleep and Stop modes register
| TIM1SMEN | TIM1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): TIM1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM1 clocks enabled by the clock gating during Sleep and Stop modes |
| SPI1SMEN | SPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): SPI1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SPI1 clocks enabled by the clock gating during Sleep and Stop modes |
| TIM8SMEN | TIM8 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): TIM8 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM8 clocks enabled by the clock gating during Sleep and Stop modes |
| USART1SMEN | USART1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): USART1clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): USART1clocks enabled by the clock gating during Sleep and Stop modes |
| TIM15SMEN | TIM15 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): TIM15 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM15 clocks enabled by the clock gating during Sleep and Stop modes |
| TIM16SMEN | TIM16 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): TIM16 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM16 clocks enabled by the clock gating during Sleep and Stop modes |
| TIM17SMEN | TIM17 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): TIM17 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM17 clocks enabled by the clock gating during Sleep and Stop modes |
| SAI1SMEN | SAI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): SAI1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SAI1 clocks enabled by the clock gating during Sleep and Stop modes |
| SAI2SMEN | SAI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series.Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): SAI2 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SAI2 clocks enabled by the clock gating during Sleep and Stop modes |
| USBSMEN | USB clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): USB clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): USB clocks enabled by the clock gating during Sleep and Stop modes |
| GFXTIMSMEN | GFXTIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): GFXTIM clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): GFXTIM clocks enabled by the clock gating during Sleep and Stop modes |
| LTDCSMEN | LTDC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): LTDC clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): LTDC clocks enabled by the clock gating during Sleep and Stop modes |
| DSISMEN | DSI clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): DSI clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): DSI clocks enabled by the clock gating during Sleep and Stop modes |