LSERDYIE=B_0x0, HSIRDYIE=B_0x0, PLL1RDYIE=B_0x0, PLL2RDYIE=B_0x0, PLL3RDYIE=B_0x0, LSIRDYIE=B_0x0, MSIKRDYIE=B_0x0, SHSIRDYIE=B_0x0, HSI48RDYIE=B_0x0, HSERDYIE=B_0x0, MSISRDYIE=B_0x0
RCC clock interrupt enable register
| LSIRDYIE | LSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization. 0 (B_0x0): LSI ready interrupt disabled 1 (B_0x1): LSI ready interrupt enabled |
| LSERDYIE | LSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. 0 (B_0x0): LSE ready interrupt disabled 1 (B_0x1): LSE ready interrupt enabled |
| MSISRDYIE | MSIS ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization. 0 (B_0x0): MSIS ready interrupt disabled 1 (B_0x1): MSIS ready interrupt enabled |
| HSIRDYIE | HSI16 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization. 0 (B_0x0): HSI16 ready interrupt disabled 1 (B_0x1): HSI16 ready interrupt enabled |
| HSERDYIE | HSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. 0 (B_0x0): HSE ready interrupt disabled 1 (B_0x1): HSE ready interrupt enabled |
| HSI48RDYIE | HSI48 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. 0 (B_0x0): HSI48 ready interrupt disabled 1 (B_0x1): HSI48 ready interrupt enabled |
| PLL1RDYIE | PLL ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL1 lock. 0 (B_0x0): PLL1 lock interrupt disabled 1 (B_0x1): PLL1 lock interrupt enabled |
| PLL2RDYIE | PLL2 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL2 lock. 0 (B_0x0): PLL2 lock interrupt disabled 1 (B_0x1): PLL2 lock interrupt enabled |
| PLL3RDYIE | PLL3 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL3 lock. 0 (B_0x0): PLL3 lock interrupt disabled 1 (B_0x1): PLL3 lock interrupt enabled |
| MSIKRDYIE | MSIK ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization. 0 (B_0x0): MSIK ready interrupt disabled 1 (B_0x1): MSIK ready interrupt enabled |
| SHSIRDYIE | SHSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization. 0 (B_0x0): SHSI ready interrupt disabled 1 (B_0x1): SHSI ready interrupt enabled |