STMicroelectronics /STM32U5A5 /SDMMC1 /MASKR

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Interpret as MASKR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CCRCFAILIE)CCRCFAILIE 0 (DCRCFAILIE)DCRCFAILIE 0 (CTIMEOUTIE)CTIMEOUTIE 0 (DTIMEOUTIE)DTIMEOUTIE 0 (TXUNDERRIE)TXUNDERRIE 0 (RXOVERRIE)RXOVERRIE 0 (CMDRENDIE)CMDRENDIE 0 (CMDSENTIE)CMDSENTIE 0 (DATAENDIE)DATAENDIE 0 (DHOLDIE)DHOLDIE 0 (DBCKENDIE)DBCKENDIE 0 (DABORTIE)DABORTIE 0 (TXFIFOHEIE)TXFIFOHEIE 0 (RXFIFOHFIE)RXFIFOHFIE 0 (RXFIFOFIE)RXFIFOFIE 0 (TXFIFOEIE)TXFIFOEIE 0 (BUSYD0ENDIE)BUSYD0ENDIE 0 (SDIOITIE)SDIOITIE 0 (ACKFAILIE)ACKFAILIE 0 (ACKTIMEOUTIE)ACKTIMEOUTIE 0 (VSWENDIE)VSWENDIE 0 (CKSTOPIE)CKSTOPIE 0 (IDMABTCIE)IDMABTCIE

Description

mask register

Fields

CCRCFAILIE

Command CRC fail interrupt enable

DCRCFAILIE

Data CRC fail interrupt enable

CTIMEOUTIE

Command timeout interrupt enable

DTIMEOUTIE

Data timeout interrupt enable

TXUNDERRIE

Tx FIFO underrun error interrupt enable

RXOVERRIE

Rx FIFO overrun error interrupt enable

CMDRENDIE

Command response received interrupt enable

CMDSENTIE

Command sent interrupt enable

DATAENDIE

Data end interrupt enable

DHOLDIE

Data hold interrupt enable

DBCKENDIE

Data block end interrupt enable

DABORTIE

Data transfer aborted interrupt enable

TXFIFOHEIE

Tx FIFO half empty interrupt enable

RXFIFOHFIE

Rx FIFO half full interrupt enable

RXFIFOFIE

Rx FIFO full interrupt enable

TXFIFOEIE

Tx FIFO empty interrupt enable

BUSYD0ENDIE

BUSYD0END interrupt enable

SDIOITIE

SDIO mode interrupt received interrupt enable

ACKFAILIE

Acknowledgment Fail interrupt enable

ACKTIMEOUTIE

Acknowledgment timeout interrupt enable

VSWENDIE

Voltage switch critical timing section completion interrupt enable

CKSTOPIE

Voltage Switch clock stopped interrupt enable

IDMABTCIE

IDMA buffer transfer complete interrupt enable

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