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STMicroelectronics /STM32U5A5 /TIM1 /DTR2

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Interpret as DTR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DTGF0 (DTAE)DTAE 0 (DTPE)DTPE

Description

deadtime register 2

Fields

DTGF

Dead-time falling edge generator setup
DTAE

Deadtime asymmetric enable
DTPE

Deadtime preload enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data