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STMicroelectronics /STM32U5A9 /ADC12_Common /ADC12_CDR2

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Interpret as ADC12_CDR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RDATA_ALT

Description

ADC common regular data register for 32-bit dual mode

Fields

RDATA_ALT

Regular data of the master/slave alternated ADCs In dual mode, these bits alternatively contains the regular 32-bit data of the master and the slave ADC. Refer to . The data alignment is applied as described in (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT).

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data