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STMicroelectronics /STM32U5A9 /DBGMCU /CIDR0

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Interpret as CIDR0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PREAMBLE

Description

Debug MCU CoreSight component identity register 0

Fields

PREAMBLE

component identification bits [7:0]

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data