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STMicroelectronics /STM32U5A9 /DSI /DSI_CCR

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Interpret as DSI_CCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TXECKDIV0TOCKDIV

Description

DSI Host clock control register

Fields

TXECKDIV

TX escape clock division This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation.
TOCKDIV

Timeout clock division This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data