UECL=B_0x0, UEDL=B_0x0, URDL=B_0x0, URCL=B_0x0
DSI Host PHY ULPS control register
| URCL | ULPS request on clock lane ULPS mode request on clock lane. 0 (B_0x0): No ULPS request 1 (B_0x1): Request ULPS mode on clock lane |
| UECL | ULPS exit on clock lane ULPS mode exit on clock lane. 0 (B_0x0): No exit request 1 (B_0x1): Exit ULPS mode on clock lane |
| URDL | ULPS request on data lane ULPS mode request on all active data lanes. 0 (B_0x0): No ULPS request 1 (B_0x1): Request ULPS mode on all active data lane UECL |
| UEDL | ULPS exit on data lane ULPS mode exit on all active data lanes. 0 (B_0x0): No exit request 1 (B_0x1): Exit ULPS mode on all active data lane URDL |