CL=B_0x0, PD=B_0x0, B3OIE=B_0x0, CE=B_0x0, B0OIE=B_0x0, CLB=B_0x0, OC=B_0x0, AMEIE=B_0x0, BM192=B_0x0, B2OIE=B_0x0, FC=B_0x0, B1OIE=B_0x0, OB=B_0x0
GFXMMU configuration register
| B0OIE | Buffer 0 overflow interrupt enable This bit enables the buffer 0 overflow interrupt. 0 (B_0x0): Interrupt disable 1 (B_0x1): Interrupt enabled |
| B1OIE | Buffer 1 overflow interrupt enable This bit enables the buffer 1 overflow interrupt. 0 (B_0x0): Interrupt disable 1 (B_0x1): Interrupt enabled |
| B2OIE | Buffer 2 overflow interrupt enable This bit enables the buffer 2 overflow interrupt. 0 (B_0x0): Interrupt disable 1 (B_0x1): Interrupt enabled |
| B3OIE | Buffer 3 overflow interrupt enable This bit enables the buffer 3 overflow interrupt. 0 (B_0x0): Interrupt disable 1 (B_0x1): Interrupt enabled |
| AMEIE | AHB master error interrupt enable This bit enables the AHB master error interrupt. 0 (B_0x0): Interrupt disable 1 (B_0x1): Interrupt enabled |
| BM192 | 192 Block mode This bit defines the number of blocks per line 0 (B_0x0): 256 blocks per line 1 (B_0x1): 192 blocks per line |
| CE | Cache enable This bit enables the cache unit. 0 (B_0x0): Cache disable 1 (B_0x1): Cache enable |
| CL | Cache lock This bit lock the cache onto the buffer defined in the CLB field. 0 (B_0x0): Cache not locked 1 (B_0x1): Cache locked to a buffer |
| CLB | Cache lock buffer This field select the buffer on which the cache is locked. 0 (B_0x0): Cache locked on buffer 0 1 (B_0x1): Cache locked on buffer 1 2 (B_0x2): Cache locked on buffer 2 3 (B_0x3): Cache locked on buffer 3 |
| FC | Force caching This bit force the caching into the cache regardless of the MPU attributes. The cache must be enable (CE bit set). 0 (B_0x0): Caching not forced 1 (B_0x1): Caching forced |
| PD | Prefetch disable This bit disables the prefetch of the cache. 0 (B_0x0): Prefetch enable 1 (B_0x1): Prefetch disable |
| OC | Outter cachability This bit configure the cachability of an access generated by the GFXMMU cache. 0 (B_0x0): No cachable 1 (B_0x1): Cachable |
| OB | Outter bufferability This bit configure the bufferability of an access generated by the GFXMMU cache. 0 (B_0x0): No bufferable 1 (B_0x1): Bufferable |