STMicroelectronics /STM32U5A9 /GFXMMU /GFXMMU_SR

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Interpret as GFXMMU_SR

Description

GFXMMU status register

Fields

B0OF	Buffer 0 overflow flag This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF.
B1OF	Buffer 1 overflow flag This bit is set when an overflow occurs during the offset calculation of the buffer 1. It is cleared by writing 1 to CB1OF.
B2OF	Buffer 2 overflow flag This bit is set when an overflow occurs during the offset calculation of the buffer 2. It is cleared by writing 1 to CB2OF.
B3OF	Buffer 3 overflow flag This bit is set when an overflow occurs during the offset calculation of the buffer 3. It is cleared by writing 1 to CB3OF.
AMEF	AHB master error flag This bit is set when an AHB error happens during a transaction. It is cleared by writing 1 to CAMEF.

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