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STMicroelectronics /STM32U5A9 /GTZC1_TZSC /TZSC_MPCWM2BCFGR

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Interpret as TZSC_MPCWM2BCFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SREN)SREN 0 (SRLOCK)SRLOCK 0 (SEC)SEC 0 (PRIV)PRIV

Description

TZSC memory 2 sub-region B watermark configuration register

Fields

SREN

Sub-region enable
SRLOCK

Sub-region lock
SEC

Secure sub-region
PRIV

Privileged sub-region

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data