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STMicroelectronics /STM32U5A9 /HSPI1 /HSPI_PIR

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Interpret as HSPI_PIR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INTERVAL

Description

HSPI polling interval register

Fields

INTERVAL

[15: 0]: Polling interval Number of CLK cycle between a read during the automatic-polling phases

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data