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STMicroelectronics /STM32U5A9 /LTDC /LTDC_ISR

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Interpret as LTDC_ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LIF 0 (B_0x0)FUIF 0 (B_0x0)TERRIF 0 (B_0x0)RRIF

LIF=B_0x0, TERRIF=B_0x0, RRIF=B_0x0, FUIF=B_0x0

Description

LTDC interrupt status register

Fields

LIF

line interrupt flag

0 (B_0x0): no line interrupt generated

1 (B_0x1): line interrupt generated when a programmed line is reached
FUIF

FIFO underrun interrupt flag

0 (B_0x0): no FIFO underrun interrupt generated.

1 (B_0x1): FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO
TERRIF

transfer error interrupt flag

0 (B_0x0): no transfer error interrupt generated

1 (B_0x1): transfer error interrupt generated when a bus error occurs
RRIF

register reload interrupt flag

0 (B_0x0): no register reload interrupt generated

1 (B_0x1): register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached)

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data