STMicroelectronics /STM32U5A9 /OTG_HS /DCFG

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Interpret as DCFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DSPD 0 (NZLSOHSK)NZLSOHSK 0DAD0PFIVL 0 (ERRATIM)ERRATIM

Description

This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.

Fields

DSPD

DSPD

NZLSOHSK

NZLSOHSK

DAD

DAD

PFIVL

PFIVL

ERRATIM

ERRATIM

Links

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