This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (GINTSTS) register bit corresponding to that interrupt is still set.
| MMISM | MMISM |
| OTGINT | OTGINT |
| SOFM | SOFM |
| RXFLVLM | RXFLVLM |
| NPTXFEM | NPTXFEM |
| GINAKEFFM | GINAKEFFM |
| GONAKEFFM | GONAKEFFM |
| ESUSPM | ESUSPM |
| USBSUSPM | USBSUSPM |
| USBRST | USBRST |
| ENUMDNEM | ENUMDNEM |
| ISOODRPM | ISOODRPM |
| EOPFM | EOPFM |
| IEPINT | IEPINT |
| OEPINT | OEPINT |
| IISOIXFRM | IISOIXFRM |
| IPXFRM | IPXFRM |
| FSUSPM | FSUSPM |
| RSTDETM | RSTDETM |
| PRTIM | PRTIM |
| HCIM | HCIM |
| PTXFEM | PTXFEM |
| LPMINTM | LPMINTM |
| CIDSCHGM | CIDSCHGM |
| DISCINT | DISCINT |
| SRQIM | SRQIM |
| WUIM | WUIM |