SAESSMEN=B_0x0, GPIOCSMEN=B_0x0, SRAM2SMEN=B_0x0, HASHSMEN=B_0x0, GPIOASMEN=B_0x0, SDMMC2SMEN=B_0x0, PKASMEN=B_0x0, SDMMC1SMEN=B_0x0, OTGSMEN=B_0x0, GPIOJSMEN=B_0x0, GPIOFSMEN=B_0x0, GPIOBSMEN=B_0x0, OTFDEC2SMEN=B_0x0, OTFDEC1SMEN=B_0x0, GPIOHSMEN=B_0x0, AESSMEN=B_0x0, DCMI_PSSISMEN=B_0x0, GPIOESMEN=B_0x0, OTGHSPHYSMEN=B_0x0, GPIOISMEN=B_0x0, OCTOSPIMSMEN=B_0x0, ADC12SMEN=B_0x0, SRAM3SMEN=B_0x0, RNGSMEN=B_0x0, GPIODSMEN=B_0x0, GPIOGSMEN=B_0x0
RCC AHB2 peripheral clock enable in Sleep and Stop modes register 1
| GPIOASMEN | I/O port A clocks enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): I/O port A clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I/O port A clocks enabled by the clock gating during Sleep and Stop modes |
| GPIOBSMEN | I/O port B clocks enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): I/O port B clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I/O port B clocks enabled by the clock gating during Sleep and Stop modes |
| GPIOCSMEN | I/O port C clocks enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): I/O port C clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I/O port C clocks enabled by the clock gating during Sleep and Stop modes |
| GPIODSMEN | I/O port D clocks enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): I/O port D clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I/O port D clocks enabled by the clock gating during Sleep and Stop modes |
| GPIOESMEN | I/O port E clocks enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): I/O port E clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I/O port E clocks enabled by the clock gating during Sleep and Stop modes |
| GPIOFSMEN | I/O port F clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): I/O port F clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I/O port F clocks enabled by the clock gating during Sleep and Stop modes |
| GPIOGSMEN | I/O port G clocks enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): I/O port G clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I/O port G clocks enabled by the clock gating during Sleep and Stop modes |
| GPIOHSMEN | I/O port H clocks enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): I/O port H clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I/O port H clocks enabled by the clock gating during Sleep and Stop modes |
| GPIOISMEN | I/O port I clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): I/O port I clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I/O port I clocks enabled by the clock gating during Sleep and Stop modes |
| GPIOJSMEN | I/O port J clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): I/O port J clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I/O port J clocks enabled by the clock gating during Sleep and Stop modes |
| ADC12SMEN | ADC1 and ADC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx. 0 (B_0x0): ADC1 and ADC2 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): ADC1 and ADC2 clocks enabled by the clock gating during Sleep and Stop modes |
| DCMI_PSSISMEN | DCMI and PSSI clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): DCMI and PSSI clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): DCMI and PSSI clocks enabled by the clock gating during Sleep and Stop modes |
| OTGSMEN | OTG_FS and OTG_HS clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): OTG_FS and OTG_HS clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): OTG_FS and OTG_HS clocks enabled by the clock gating during Sleep and Stop modes |
| OTGHSPHYSMEN | OTG_HS PHY clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): OTG_HS PHY clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): OTG_HS PHY clocks enabled by the clock gating during Sleep and Stop modes |
| AESSMEN | AES clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): AES clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): AES clocks enabled by the clock gating during Sleep and Stop modes |
| HASHSMEN | HASH clock enable during Sleep and Stop modes This bit is set and cleared by software 0 (B_0x0): HASH clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): HASH clocks enabled by the clock gating during Sleep and Stop modes |
| RNGSMEN | RNG clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): RNG clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): RNG clocks enabled by the clock gating during Sleep and Stop modes |
| PKASMEN | PKA clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): PKA clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): PKA clocks enabled by the clock gating during Sleep and Stop modes |
| SAESSMEN | SAES accelerator clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): SAES clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SAES clocks enabled by the clock gating during Sleep and Stop modes |
| OCTOSPIMSMEN | OCTOSPIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): OCTOSPIM clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): OCTOSPIM clocks enabled by the clock gating during Sleep and Stop modes |
| OTFDEC1SMEN | OTFDEC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): OTFDEC1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): OTFDEC1 clocks enabled by the clock gating during Sleep and Stop modes |
| OTFDEC2SMEN | OTFDEC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): OTFDEC2 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): OTFDEC2 clocks enabled by the clock gating during Sleep and Stop modes |
| SDMMC1SMEN | SDMMC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): SDMMC1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SDMMC1 clocks enabled by the clock gating during Sleep and Stop modes |
| SDMMC2SMEN | SDMMC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): SDMMC2 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SDMMC2 clocks enabled by the clock gating during Sleep and Stop modes |
| SRAM2SMEN | SRAM2 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): SRAM2 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SRAM2 clocks enabled by the clock gating during Sleep and Stop modes |
| SRAM3SMEN | SRAM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): SRAM3 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SRAM3 clocks enabled by the clock gating during Sleep and Stop modes |