RegViz: Visualize RCC_APB1RSTR1 Bitfield

STMicroelectronics /STM32U5A9 /RCC /RCC_APB1RSTR1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RCC_APB1RSTR1

TIM7RST=B_0x0, TIM5RST=B_0x0, SPI2RST=B_0x0, USART3RST=B_0x0, I2C2RST=B_0x0, TIM4RST=B_0x0, CRSRST=B_0x0, UART4RST=B_0x0, USART6RST=B_0x0, TIM3RST=B_0x0, UART5RST=B_0x0, I2C1RST=B_0x0, TIM2RST=B_0x0, USART2RST=B_0x0, TIM6RST=B_0x0

Description

RCC APB1 peripheral reset register 1

Fields

TIM2RST	TIM2 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the TIM2.
TIM3RST	TIM3 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the TIM3.
TIM4RST	TIM4 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the TIM4.
TIM5RST	TIM5 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the TIM5.
TIM6RST	TIM6 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the TIM6.
TIM7RST	TIM7 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the TIM7.
SPI2RST	SPI2 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the SPI2.
USART2RST	USART2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series.Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the USART2
USART3RST	USART3 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the USART3.
UART4RST	UART4 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the UART4.
UART5RST	UART5 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the UART5.
I2C1RST	I2C1 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the I2C1.
I2C2RST	I2C2 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the I2C2.
CRSRST	CRS reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the CRS.
USART6RST	USART6 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the USART6.

Links

()