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STMicroelectronics /STM32U5A9 /RCC /RCC_SRDAMR

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Interpret as RCC_SRDAMR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SPI3AMEN 0 (B_0x0)LPUART1AMEN 0 (B_0x0)I2C3AMEN 0 (B_0x0)LPTIM1AMEN 0 (B_0x0)LPTIM3AMEN 0 (B_0x0)LPTIM4AMEN 0 (B_0x0)OPAMPAMEN 0 (B_0x0)COMPAMEN 0 (B_0x0)VREFAMEN 0 (B_0x0)RTCAPBAMEN 0 (B_0x0)ADC4AMEN 0 (B_0x0)LPGPIO1AMEN 0 (B_0x0)DAC1AMEN 0 (B_0x0)LPDMA1AMEN 0 (B_0x0)ADF1AMEN 0 (B_0x0)SRAM4AMEN

DAC1AMEN=B_0x0, RTCAPBAMEN=B_0x0, OPAMPAMEN=B_0x0, LPTIM3AMEN=B_0x0, SRAM4AMEN=B_0x0, LPGPIO1AMEN=B_0x0, SPI3AMEN=B_0x0, LPUART1AMEN=B_0x0, ADC4AMEN=B_0x0, LPTIM1AMEN=B_0x0, LPTIM4AMEN=B_0x0, I2C3AMEN=B_0x0, VREFAMEN=B_0x0, LPDMA1AMEN=B_0x0, COMPAMEN=B_0x0, ADF1AMEN=B_0x0

Description

RCC SmartRun domain peripheral autonomous mode register

Fields

SPI3AMEN

SPI3 autonomous mode enable in Stop 0,1, 2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.

0 (B_0x0): SPI3 autonomous mode disabled during Stop 0/1/2 mode

1 (B_0x1): SPI3 autonomous mode enabled during Stop 0/1/2 mode
LPUART1AMEN

LPUART1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.

0 (B_0x0): LPUART1 autonomous mode disabled during Stop 0/1/2 mode

1 (B_0x1): LPUART1 autonomous mode enabled during Stop 0/1/2 mode
I2C3AMEN

I2C3 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.

0 (B_0x0): I2C3 autonomous mode disabled during Stop 0/1/2 mode

1 (B_0x1): I2C3 autonomous mode enabled during Stop 0/1/2 mode
LPTIM1AMEN

LPTIM1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.

0 (B_0x0): LPTIM1 autonomous mode disabled during Stop 0/1/2 mode

1 (B_0x1): LPTIM1 autonomous mode enabled during Stop 0/1/2 mode
LPTIM3AMEN

LPTIM3 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.

0 (B_0x0): LPTIM3 autonomous mode disabled during Stop 0/1/2 mode

1 (B_0x1): LPTIM3 autonomous mode enabled during Stop 0/1/2 mode
LPTIM4AMEN

LPTIM4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.

0 (B_0x0): LPTIM4 autonomous mode disabled during Stop 0/1/2 mode

1 (B_0x1): LPTIM4 autonomous mode enabled during Stop 0/1/2 mode
OPAMPAMEN

OPAMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software.

0 (B_0x0): OPAMP autonomous mode disabled during Stop 0/1/2 mode

1 (B_0x1): OPAMP autonomous mode enabled during Stop 0/1/2 mode
COMPAMEN

COMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software.

0 (B_0x0): COMP autonomous mode disabled during Stop 0/1/2 mode

1 (B_0x1): COMP autonomous mode enabled during Stop 0/1/2 mode
VREFAMEN

VREFBUF autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software.

0 (B_0x0): VREFBUF autonomous mode disabled during Stop 0/1/2 mode

1 (B_0x1): VREFBUF autonomous mode enabled during Stop 0/1/2 mode
RTCAPBAMEN

RTC and TAMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.

0 (B_0x0): RTC and TAMP autonomous mode disabled during Stop 0/1/2mode

1 (B_0x1): RTC and TAMP autonomous mode enabled during Stop 0/1/2 mode
ADC4AMEN

ADC4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.

0 (B_0x0): ADC4 autonomous mode disabled during Stop 0/1/2 mode

1 (B_0x1): ADC4 autonomous mode enabled during Stop 0/1/2 mode
LPGPIO1AMEN

LPGPIO1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software.

0 (B_0x0): LPGPIO1 autonomous mode disabled during Stop 0/1/2 mode

1 (B_0x1): LPGPIO1 autonomous mode enabled during Stop 0/1/2 mode
DAC1AMEN

DAC1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.

0 (B_0x0): DAC1 autonomous mode disabled during Stop 0/1/2 mode

1 (B_0x1): DAC1 autonomous mode enabled during Stop 0/1/2 mode
LPDMA1AMEN

LPDMA1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.

0 (B_0x0): LPDMA1 autonomous mode disabled during Stop 0/1/2 mode

1 (B_0x1): LPDMA1 autonomous mode enabled during Stop 0/1/2 mode
ADF1AMEN

ADF1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.

0 (B_0x0): ADF1 autonomous mode disabled during Stop 0/1/2 mode

1 (B_0x1): ADF1 autonomous mode enabled during Stop 0/1/2 mode
SRAM4AMEN

SRAM4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software.

0 (B_0x0): SRAM4 autonomous mode disabled during Stop 0/1/2 mode

1 (B_0x1): SRAM4 autonomous mode enabled during Stop 0/1/2 mode

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data