status register
| CCRCFAIL | Command response received (CRC check failed) |
| DCRCFAIL | Data block sent/received (CRC check failed) |
| CTIMEOUT | Command response timeout |
| DTIMEOUT | Data timeout |
| TXUNDERR | Transmit FIFO underrun error (masked by hardware when IDMA is enabled) |
| RXOVERR | Received FIFO overrun error (masked by hardware when IDMA is enabled) |
| CMDREND | Command response received (CRC check passed, or no CRC) |
| CMDSENT | Command sent (no response required) |
| DATAEND | Data transfer ended correctly |
| DHOLD | Data transfer Hold |
| DBCKEND | Data block sent/received |
| DABORT | Data transfer aborted by CMD12 |
| DPSMACT | Data path state machine active, i.e. not in Idle state |
| CPSMACT | Command path state machine active, i.e. not in Idle state |
| TXFIFOHE | Transmit FIFO half empty |
| RXFIFOHF | Receive FIFO half full |
| TXFIFOF | Transmit FIFO full |
| RXFIFOF | Receive FIFO full |
| TXFIFOE | Transmit FIFO empty |
| RXFIFOE | Receive FIFO empty |
| BUSYD0 | Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response |
| BUSYD0END | end of SDMMC_D0 Busy following a CMD response detected |
| SDIOIT | SDIO interrupt received |
| ACKFAIL | Boot acknowledgment received (boot acknowledgment check fail) |
| ACKTIMEOUT | Boot acknowledgment timeout |
| VSWEND | Voltage switch critical timing section completion |
| CKSTOP | SDMMC_CK stopped in Voltage switch procedure |
| IDMATE | IDMA transfer error |
| IDMABTC | IDMA buffer transfer complete |