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STMicroelectronics /STM32U5A9 /SYSCFG /CFGR2

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Interpret as CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLL)CLL 0 (SPL)SPL 0 (PVDL)PVDL 0 (ECCL)ECCL

Description

configuration register 2

Fields

CLL

LOCKUP (hardfault) output enable bit
SPL

SRAM ECC lock bit
PVDL

PVD lock enable bit
ECCL

ECC Lock

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data