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STMicroelectronics /STM32U5A9 /TIM2 /SMCR

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Interpret as SMCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SMS0 (OCCS)OCCS 0TS_2_0 0 (MSM)MSM 0ETF0ETPS 0 (ECE)ECE 0 (ETP)ETP 0 (SMS_bit3)SMS_bit3 0TS_4_3 0 (SMSPE)SMSPE 0 (SMSPS)SMSPS

Description

slave mode control register

Fields

SMS

Slave mode selection
OCCS

OCREF clear selection
TS_2_0

Trigger selection
MSM

Master/Slave mode
ETF

External trigger filter
ETPS

External trigger prescaler
ECE

External clock enable
ETP

External trigger polarity
SMS_bit3

Slave mode selection - bit 3
TS_4_3

Trigger selection
SMSPE

SMS preload enable
SMSPS

SMS preload source

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data