DUAL=B_0x0, VBATEN=B_0x0, VREFEN=B_0x0, PRESC=B_0x0, DAMDF=B_0x0, VSENSESEL=B_0x0
ADC_CCR system control register
| DUAL | Dual ADC mode selection These bits are written by software to select the operating mode. All the ADCs are independent: The configurations 00001 to 01001 correspond to the following operating modes: Dual mode, master and slave ADCs working together: All other combinations are reserved and must not be programmed Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 0 (B_0x0): Independent mode 1 (B_0x1): Combined regular simultaneous + injected simultaneous mode 2 (B_0x2): Combined regular simultaneous + alternate trigger mode 3 (B_0x3): Combined Interleaved mode + injected simultaneous mode 5 (B_0x5): Injected simultaneous mode only 6 (B_0x6): Regular simultaneous mode only 7 (B_0x7): Interleaved mode only 9 (B_0x9): Alternate trigger mode only |
| DELAY | Delay between the end of the master ADC sampling phase and the beginning of the slave ADC sampling phase. These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to for the value of ADC resolution versus DELAY bits values. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). |
| DAMDF | Dual ADC Mode Data Format This bit-field is set and cleared by software. It specifies the data format in the common data register ADC12_CDR. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 0 (B_0x0): Dual ADC mode without data packing (ADC12_CDR and ADC12_CDR2 registers not used). 2 (B_0x2): Data formatting mode for 32 down to 10-bit resolution 3 (B_0x3): Data formatting mode for 8-bit resolution |
| PRESC | ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 0 (B_0x0): input ADC clock not divided 1 (B_0x1): input ADC clock divided by 2 2 (B_0x2): input ADC clock divided by 4 3 (B_0x3): input ADC clock divided by 6 4 (B_0x4): input ADC clock divided by 8 5 (B_0x5): input ADC clock divided by 10 6 (B_0x6): input ADC clock divided by 12 7 (B_0x7): input ADC clock divided by 16 8 (B_0x8): input ADC clock divided by 32 9 (B_0x9): input ADC clock divided by 64 10 (B_0xA): input ADC clock divided by 128 11 (B_0xB): input ADC clock divided by 256 |
| VREFEN | VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 0 (B_0x0): VREFINT channel disabled 1 (B_0x1): VREFINT channel enabled |
| VSENSESEL | Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 0 (B_0x0): Temperature sensor channel disabled 1 (B_0x1): Temperature sensor channel enabled |
| VBATEN | VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 0 (B_0x0): VBAT channel disabled 1 (B_0x1): VBAT channel enabled |