DPCC=B_0x0, ACR=B_0x0
DSI Host clock lane configuration register
| DPCC | D-PHY clock control This bit controls the D-PHY clock state: 0 (B_0x0): Clock lane is in low-power mode. 1 (B_0x1): Clock lane runs in high-speed mode. |
| ACR | Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows. 0 (B_0x0): Automatic clock lane control disabled 1 (B_0x1): Automatic clock lane control enabled |