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STMicroelectronics /STM32U5Fx /DSI /DSI_PCONFR

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Interpret as DSI_PCONFR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)NL0SW_TIME

NL=B_0x0

Description

DSI Host PHY configuration register

Fields

NL

Number of lanes This field configures the number of active data lanes: Others: Reserved

0 (B_0x0): One data lane (lane 0)

1 (B_0x1): Two data lanes (lanes 0 and 1) - Reset value
SW_TIME

Stop wait time This field configures the minimum wait period to request a high-speed transmission after the Stop state.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data