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STMicroelectronics /STM32U5Fx /DSI /DSI_PCTLR

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Interpret as DSI_PCTLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DEN 0 (B_0x0)CKE

DEN=B_0x0, CKE=B_0x0

Description

DSI Host PHY control register

Fields

DEN

Digital enable When set to 0, this bit places the digital section of the D-PHY in the reset state

0 (B_0x0): The digital section of the D-PHY is in the reset state.

1 (B_0x1): The digital section of the D-PHY is enabled.
CKE

Clock enable This bit enables the D-PHY clock lane module:

0 (B_0x0): D-PHY clock lane module is disabled.

1 (B_0x1): D-PHY clock lane module is enabled.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data