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STMicroelectronics /STM32U5Fx /DSI /DSI_TCCR4

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Interpret as DSI_TCCR4

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LPWR_TOCNT

Description

DSI Host timeout counter configuration register 4

Fields

LPWR_TOCNT

Low-power write timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data