STMicroelectronics /STM32U5Fx /DSI /DSI_WISR

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Interpret as DSI_WISR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TEIF 0 (B_0x0)ERIF 0 (B_0x0)BUSY 0 (B_0x0)PLLLS 0 (B_0x0)PLLLIF 0 (B_0x0)PLLUIF

PLLLS=B_0x0, BUSY=B_0x0, PLLUIF=B_0x0, PLLLIF=B_0x0, ERIF=B_0x0, TEIF=B_0x0

Description

DSI Wrapper interrupt and status register

Fields

TEIF

Tearing effect interrupt flag This bit is set when a tearing effect event occurs.

0 (B_0x0): No tearing effect event occurred

1 (B_0x1): Tearing effect event occurred

ERIF

End of refresh interrupt flag This bit is set when the transfer of a frame in adapted command mode is finished.

0 (B_0x0): No end of refresh event occurred

1 (B_0x1): End of refresh event occurred

BUSY

Busy flag This bit is set when the transfer of a frame in adapted command mode is ongoing.

0 (B_0x0): No transfer on going

1 (B_0x1): Transfer on going

PLLLS

PLL lock status This bit is set when the PLL is locked and cleared when it is unlocked.

0 (B_0x0): PLL is unlocked.

1 (B_0x1): PLL is locked.

PLLLIF

PLL lock interrupt flag This bit is set when the PLL becomes locked.

0 (B_0x0): No PLL lock event occurred

1 (B_0x1): PLL lock event occurred

PLLUIF

PLL unlock interrupt flag This bit is set when the PLL becomes unlocked.

0 (B_0x0): No PLL unlock event occurred

1 (B_0x1): PLL unlock event occurred

Links

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