SWDL0=B_0x0, SWDL1=B_0x0, FTXSMCL=B_0x0, FTXSMDL=B_0x0, SWCL=B_0x0
DSI Wrapper PHY configuration register 0
| SWCL | Swap clock lane pins This bit swaps the pins on clock lane. 0 (B_0x0): Regular clock lane pin configuration 1 (B_0x1): Swapped clock lane pin |
| SWDL0 | Swap data lane 0 pins This bit swaps the pins on data lane 0. 0 (B_0x0): Regular clock lane pin configuration 1 (B_0x1): Swapped clock lane pin |
| SWDL1 | Swap data lane 1 pins This bit swaps the pins on clock lane. 0 (B_0x0): Regular clock lane pin configuration 1 (B_0x1): Swapped clock lane pin |
| FTXSMCL | Force in TX Stop mode the clock lane This bit forces the clock lane in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence. 0 (B_0x0): No effect 1 (B_0x1): Force the clock lane in TX Stop mode |
| FTXSMDL | Force in TX Stop mode the data lanes This bit forces the data lanes in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence. 0 (B_0x0): No effect 1 (B_0x1): Force the data lanes in TX Stop mode |