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STMicroelectronics /STM32U5Fx /GFXMMU /GFXMMU_CCR

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Interpret as GFXMMU_CCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)FF 0 (B_0x0)FI

FI=B_0x0, FF=B_0x0

Description

GFXMMU cache control register

Fields

FF

Force flush When set, the cache entries are flushed. This bit is reset by hardware when the flushing is complete. Write 0 has no effect.

0 (B_0x0): Flushing process complete

1 (B_0x1): Force flush/flushing process on going
FI

Force invalidate When set, the cache entries are invalidated. This bit is reset by hardware when the invalidation is complete. Write 0 has no effect.

0 (B_0x0): Invalidation process complete

1 (B_0x1): Force invalidation/invalidation process on going

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data