STMicroelectronics /STM32U5Fx /HSPI1 /HSPI_CR

Enable This bit enables the HSPI. Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. In case this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active.

0 (B_0x0): HSPI disabled

1 (B_0x1): HSPI enabled

Abort request This bit aborts the on-going command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0.

0 (B_0x0): No abort requested

1 (B_0x1): Abort requested

DMA enable In Indirect mode, the DMA can be used to input or output data via HSPI_DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write this bit during DMA operation.

0 (B_0x0): DMA disabled for Indirect mode

1 (B_0x1): DMA enabled for Indirect mode

Timeout counter enable This bit is valid only when the Memory-mapped mode (FMODE[1:0] = 11) is selected. This bit enables the timeout counter.

0 (B_0x0): Timeout counter is disabled, and thus the chip-select (nCS) remains active indefinitely after an access in Memory-mapped mode.

1 (B_0x1): Timeout counter is enabled, and thus the chip-select is released in the Memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity.

Dual-memory mode This bit activates the Dual-memory mode, where two external devices are used simultaneously to double the throughput and the capacity

0 (B_0x0): Dual-quad mode disabled

1 (B_0x1): Dual-quad mode enabled

Memory select This bit is the mirror of bit 30. Refer to the description of MSEL[1:0] above. This bit is set when 1 is written in bit 30 or bit 7. When this bit is set, both b30 and b7 are read as 1. This bit is reset when bit 30 and bit7 are set to 0. When this bit is reset, both bit 30 and bit7 are read as 0.

FIFO threshold level This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in HSPI_SR, to be set. … Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[5:0] value.

0 (B_0x0): FTF is set if there are one or more free bytes available to be written to in the FIFO in Indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in Indirect-read mode.

1 (B_0x1): FTF is set if there are two or more free bytes available to be written to in the FIFO in Indirect-write mode, or if there are two or more valid bytes can be read from the FIFO in Indirect-read mode.

63 (B_0x3F): FTF is set if there are 64 free bytes available to be written to in the FIFO in Indirect-write mode, or if there are 64 valid bytes can be read from the FIFO in Indirect-read mode.

Transfer error interrupt enable This bit enables the transfer error interrupt.

0 (B_0x0): Interrupt disabled

1 (B_0x1): Interrupt enabled

Transfer complete interrupt enable This bit enables the transfer complete interrupt.

0 (B_0x0): Interrupt disabled

1 (B_0x1): Interrupt enabled

FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt.

0 (B_0x0): Interrupt disabled

1 (B_0x1): Interrupt enabled

Status match interrupt enable This bit enables the status match interrupt.

0 (B_0x0): Interrupt disabled

1 (B_0x1): Interrupt enabled

Timeout interrupt enable This bit enables the timeout interrupt.

0 (B_0x0): Interrupt disabled

1 (B_0x1): Interrupt enabled

Automatic-polling mode stop This bit determines if the automatic polling is stopped after a match.

0 (B_0x0): Automatic-polling mode is stopped only by abort or by disabling the HSPI.

1 (B_0x1): Automatic-polling mode stops as soon as there is a match.

Polling match mode This bit indicates which method must be used to determine a match during the Automatic-polling mode.

0 (B_0x0): AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register.

1 (B_0x1): OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register.

Functional mode This field defines the HSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state.

0 (B_0x0): Indirect-write mode

1 (B_0x1): Indirect-read mode

2 (B_0x2): Automatic-polling mode

3 (B_0x3): Memory-mapped mode

Flash select These bits select the memory to be addressed in Single, Dual, Quad or Octal mode in single‑memory configuration (when DMM = 0).

• when in Quad mode:
• when in Octal mode or Dual-quad mode: 0x: data exchanged over IO[7:0] 1x: data exchanged over IO[15:8] These bits are ignored when in dual-octal configuration (data on 8 bits and DMM = 1) or 16‑bit configuration (data exchanged over IO[15:0]).

0 (B_0x0): data exchanged over IO[3:0]

1 (B_0x1): data exchanged over IO[7:4]

2 (B_0x2): data exchanged over IO11:8]

3 (B_0x3): data exchanged over IO[15:12]