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STMicroelectronics /STM32U5Fx /HSPI1 /HSPI_WPTCR

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Interpret as HSPI_WPTCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DCYC0 (B_0x0)DHQC 0 (B_0x0)SSHIFT

SSHIFT=B_0x0, DHQC=B_0x0

Description

HSPI wrap timing configuration register

Fields

DCYC

Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated.
DHQC

Delay hold quarter cycle Add a quarter cycle delay on the outputs in DTR communication to match hold requirement.

0 (B_0x0): No quarter cycle delay

1 (B_0x1): Quarter cycle delay inserted
SSHIFT

Sample shift By default, the HSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode (when DDTR = 1).

0 (B_0x0): No shift

1 (B_0x1): 1/2 cycle shift

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data