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STMicroelectronics /STM32U5Fx /LTDC /LTDC_GCR

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Interpret as LTDC_GCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LTDCEN 0DBW0DGW0DRW0 (B_0x0)DEN 0 (B_0x0)PCPOL 0 (B_0x0)DEPOL 0 (B_0x0)VSPOL 0 (B_0x0)HSPOL

PCPOL=B_0x0, VSPOL=B_0x0, DEN=B_0x0, LTDCEN=B_0x0, HSPOL=B_0x0, DEPOL=B_0x0

Description

LTDC global control register

Fields

LTDCEN

LCD-TFT controller enable This bit is set and cleared by software.

0 (B_0x0): LTDC disabled

1 (B_0x1): LTDC enabled
DBW

dither blue width These bits return the dither blue bits.
DGW

dither green width These bits return the dither green bits.
DRW

dither red width These bits return the Dither Red Bits.
DEN

dither enable This bit is set and cleared by software.

0 (B_0x0): dither disabled

1 (B_0x1): dither enabled
PCPOL

pixel clock polarity This bit is set and cleared by software.

0 (B_0x0): pixel clock polarity is active low.

1 (B_0x1): pixel clock is active high.
DEPOL

not data enable polarity This bit is set and cleared by software.

0 (B_0x0): not data enable polarity is active low.

1 (B_0x1): not data enable polarity is active high.
VSPOL

vertical synchronization polarity This bit is set and cleared by software.

0 (B_0x0): vertical synchronization is active low.

1 (B_0x1): vertical synchronization is active high.
HSPOL

horizontal synchronization polarity This bit is set and cleared by software.

0 (B_0x0): horizontal synchronization polarity is active low.

1 (B_0x1): horizontal synchronization polarity is active high.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data