STMicroelectronics /STM32U5Fx /OTG_HS /HPRT

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Interpret as HPRT

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PCSTS)PCSTS 0 (PCDET)PCDET 0 (PENA)PENA 0 (PENCHNG)PENCHNG 0 (POCA)POCA 0 (POCCHNG)POCCHNG 0 (PRES)PRES 0 (PSUSP)PSUSP 0 (PRST)PRST 0PLSTS 0 (PPWR)PPWR 0PTCTL0PSPD

Description

This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.

Fields

PCSTS

PCSTS

PCDET

PCDET

PENA

PENA

PENCHNG

PENCHNG

POCA

POCA

POCCHNG

POCCHNG

PRES

PRES

PSUSP

PSUSP

PRST

PRST

PLSTS

PLSTS

PPWR

PPWR

PTCTL

PTCTL

PSPD

PSPD

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