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STMicroelectronics /STM32U5Fx /PWR /PWR_CR2

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Interpret as PWR_CR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SRAM1PDS1 0 (B_0x0)SRAM1PDS2 0 (B_0x0)SRAM1PDS3 0 (B_0x0)SRAM2PDS1 0 (B_0x0)SRAM2PDS2 0 (B_0x0)SRAM4PDS 0 (B_0x0)DC2RAMPDS 0 (B_0x0)ICRAMPDS 0 (B_0x0)DC1RAMPDS 0 (B_0x0)DMA2DRAMPDS 0 (B_0x0)PRAMPDS 0 (B_0x0)SRAM4FWU 0 (B_0x0)FLASHFWU 0 (B_0x0)SRAM3PDS1 0 (B_0x0)SRAM3PDS2 0 (B_0x0)SRAM3PDS3 0 (B_0x0)SRAM3PDS4 0 (B_0x0)SRAM3PDS5 0 (B_0x0)SRAM3PDS6 0 (B_0x0)SRAM3PDS7 0 (B_0x0)SRAM3PDS8 0 (B_0x0)GPRAMPDS 0 (B_0x0)DSIRAMPDS 0 (B_0x0)SRDRUN

SRAM3PDS8=B_0x0, SRAM4FWU=B_0x0, SRAM3PDS6=B_0x0, DC1RAMPDS=B_0x0, DC2RAMPDS=B_0x0, SRDRUN=B_0x0, DMA2DRAMPDS=B_0x0, FLASHFWU=B_0x0, SRAM4PDS=B_0x0, DSIRAMPDS=B_0x0, ICRAMPDS=B_0x0, SRAM3PDS5=B_0x0, PRAMPDS=B_0x0, SRAM3PDS3=B_0x0, SRAM2PDS2=B_0x0, SRAM3PDS7=B_0x0, SRAM3PDS1=B_0x0, SRAM2PDS1=B_0x0, SRAM3PDS4=B_0x0, SRAM1PDS1=B_0x0, SRAM1PDS3=B_0x0, SRAM3PDS2=B_0x0, GPRAMPDS=B_0x0, SRAM1PDS2=B_0x0

Description

PWR control register 2

Fields

SRAM1PDS1

SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): SRAM1 page 1 content retained in Stop modes

1 (B_0x1): SRAM1 page 1 content lost in Stop modes
SRAM1PDS2

SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): SRAM1 page 2 content retained in Stop modes

1 (B_0x1): SRAM1 page 2 content lost in Stop modes
SRAM1PDS3

SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): SRAM1 page 3 content retained in Stop modes

1 (B_0x1): SRAM1 page 3 content lost in Stop modes
SRAM2PDS1

SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 1 retention in Stop 3 is controlled by RRSB1 bit in PWR_CR1.

0 (B_0x0): SRAM2 page 1 content retained in Stop modes

1 (B_0x1): SRAM2 page 1 content lost in Stop modes
SRAM2PDS2

SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 2 retention in Stop 3 is controlled by RRSB2 bit in PWR_CR1.

0 (B_0x0): SRAM2 page 2 content retained in Stop modes

1 (B_0x1): SRAM2 page 2 content lost in Stop modes
SRAM4PDS

SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): SRAM4 content retained in Stop modes

1 (B_0x1): SRAM4 content lost in Stop modes
DC2RAMPDS

DCACHE2 SRAM power-down in Stop modes (Stop 0, 1, 2, 3) Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585.

0 (B_0x0): DCACHE2 SRAM content retained in Stop modes

1 (B_0x1): DCACHE2 SRAM content lost in Stop modes
ICRAMPDS

ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): ICACHE SRAM content retained in Stop modes

1 (B_0x1): ICACHE SRAM content lost in Stop modes
DC1RAMPDS

DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): DCACHE1 SRAM content retained in Stop modes

1 (B_0x1): DCACHE1 SRAM content lost in Stop modes
DMA2DRAMPDS

DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): DMA2D SRAM content retained in Stop modes

1 (B_0x1): DMA2D SRAM content lost in Stop modes
PRAMPDS

FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): FMAC, FDCAN and USB peripherals SRAM content retained in Stop modes

1 (B_0x1): FMAC, FDCAN and USB peripherals SRAM content lost in Stop modes
SRAM4FWU

SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting Stop 0, 1 and 2 modes, and also increases the LPDMA access time to SRAM4 during Stop modes.

0 (B_0x0): SRAM4 enters low-power mode in Stop 0, 1 and 2 modes (source biasing for lower-power consumption).

1 (B_0x1): SRAM4 remains in normal mode in Stop 0, 1 and 2 modes (higher consumption but no SRAM4 wakeup time).
FLASHFWU

Flash memory fast wakeup from Stop 0 and Stop 1 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption.

0 (B_0x0): Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption).

1 (B_0x1): Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time).
SRAM3PDS1

SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): SRAM3 page 1 content retained in Stop modes

1 (B_0x1): SRAM3 page 1 content lost in Stop modes
SRAM3PDS2

SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): SRAM3 page 2 content retained in Stop modes

1 (B_0x1): SRAM3 page 2 content lost in Stop modes
SRAM3PDS3

SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): SRAM3 page 3 content retained in Stop modes

1 (B_0x1): SRAM3 page 3 content lost in Stop modes
SRAM3PDS4

SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): SRAM3 page 4 content retained in Stop modes

1 (B_0x1): SRAM3 page 4 content lost in Stop modes
SRAM3PDS5

SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): SRAM3 page 5 content retained in Stop modes

1 (B_0x1): SRAM3 page 5 content lost in Stop modes
SRAM3PDS6

SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): SRAM3 page 6 content retained in Stop modes

1 (B_0x1): SRAM3 page 6 content lost in Stop modes
SRAM3PDS7

SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): SRAM3 page 7 content retained in Stop modes

1 (B_0x1): SRAM3 page 7 content lost in Stop modes
SRAM3PDS8

SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)

0 (B_0x0): SRAM3 page 8 content retained in Stop modes

1 (B_0x1): SRAM3 page 8 content lost in Stop modes
GPRAMPDS

Graphic peripherals (LTDC, GFXMMU) SRAM power-down in Stop modes (Stop 0, 1, 2, 3) Note: LTDC SRAM content is always lost in Stop 2 and Stop 3 modes. It can be retained only in Stop 0 and Stop 1 modes. This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585.

0 (B_0x0): Graphic peripherals SRAM content retained in Stop modes

1 (B_0x1): Graphic peripherals SRAM content lost in Stop modes
DSIRAMPDS

DSI SRAM power-down in Stop modes (Stop 0, 1) DSI SRAM content is always lost in Stop 2 and Stop 3 modes. Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585.

0 (B_0x0): DSI SRAM content retained in Stop 0 and Stop 1 modes

1 (B_0x1): DSI SRAM content lost in Stop 0 and Stop 1 modes
SRDRUN

SmartRun domain in Run mode

0 (B_0x0): SmartRun domain AHB3 and APB3 clocks disabled by default in Stop 0,1, 2 modes

1 (B_0x1): SmartRun domain AHB3 and APB3 clocks kept enabled in Stop 0,1, 2 modes

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data