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STMicroelectronics /STM32U5Fx /PWR /PWR_DBPR

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Interpret as PWR_DBPR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DBP

DBP=B_0x0

Description

PWR disable Backup domain register

Fields

DBP

Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers.

0 (B_0x0): Write access to Backup domain disabled

1 (B_0x1): Write access to Backup domain enabled

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data