DMA2DEN=B_0x0, SRAM1EN=B_0x0, GTZC1EN=B_0x0, FMACEN=B_0x0, CORDICEN=B_0x0, JPEGEN=B_0x0, FLASHEN=B_0x0, BKPSRAMEN=B_0x0, TSCEN=B_0x0, GPU2DEN=B_0x0, MDF1EN=B_0x0, DCACHE1EN=B_0x0, GFXMMUEN=B_0x0, DCACHE2EN=B_0x0, GPDMA1EN=B_0x0, RAMCFGEN=B_0x0, CRCEN=B_0x0
RCC AHB1 peripheral clock enable register
| GPDMA1EN | GPDMA1 clock enable This bit is set and cleared by software. 0 (B_0x0): GPDMA1 clock disabled 1 (B_0x1): GPDMA1 clock enabled |
| CORDICEN | CORDIC clock enable This bit is set and cleared by software. 0 (B_0x0): CORDIC clock disabled 1 (B_0x1): CORDIC clock enabled |
| FMACEN | FMAC clock enable This bit is set and reset by software. 0 (B_0x0): FMAC clock disabled 1 (B_0x1): FMAC clock enabled |
| MDF1EN | MDF1 clock enable This bit is set and reset by software. 0 (B_0x0): MDF1 clock disabled 1 (B_0x1): MDF1 clock enabled |
| FLASHEN | FLASH clock enable This bit is set and cleared by software. This bit can be disabled only when the flash memory is in power-down mode. 0 (B_0x0): FLASH clock disabled 1 (B_0x1): FLASH clock enabled |
| CRCEN | CRC clock enable This bit is set and cleared by software. 0 (B_0x0): CRC clock disabled 1 (B_0x1): CRC clock enabled |
| JPEGEN | JPEG clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): JPEG clock disabled 1 (B_0x1): JPEG clock enabled |
| TSCEN | Touch sensing controller clock enable This bit is set and cleared by software. 0 (B_0x0): TSC clock disabled 1 (B_0x1): TSC clock enabled |
| RAMCFGEN | RAMCFG clock enable This bit is set and cleared by software. 0 (B_0x0): RAMCFG clock disabled 1 (B_0x1): RAMCFG clock enabled |
| DMA2DEN | DMA2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): DMA2D clock disabled 1 (B_0x1): DMA2D clock enabled |
| GFXMMUEN | GFXMMU clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): GFXMMU clock disabled 1 (B_0x1): GFXMMU clock enabled |
| GPU2DEN | GPU2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): GPU2D clock disabled 1 (B_0x1): GPU2D clock enabled |
| DCACHE2EN | DCACHE2 clock enable This bit is set and reset by software. Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): DCACHE2 clock disabled 1 (B_0x1): DCACHE2 clock enabled |
| GTZC1EN | GTZC1 clock enable This bit is set and reset by software. 0 (B_0x0): GTZC1 clock disabled 1 (B_0x1): GTZC1 clock enabled |
| BKPSRAMEN | BKPSRAM clock enable This bit is set and reset by software. 0 (B_0x0): BKPSRAM clock disabled 1 (B_0x1): BKPSRAM clock enabled |
| DCACHE1EN | DCACHE1 clock enable This bit is set and reset by software. Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2, HSPI1 or FSMC, even if the DCACHE1 is bypassed. 0 (B_0x0): DCACHE1 clock disabled 1 (B_0x1): DCACHE1 clock enabled |
| SRAM1EN | SRAM1 clock enable This bit is set and reset by software. 0 (B_0x0): SRAM1 clock disabled 1 (B_0x1): SRAM1 clock enabled |