RegViz: Visualize RCC_AHB1RSTR Bitfield

STMicroelectronics /STM32U5Fx /RCC /RCC_AHB1RSTR

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Interpret as RCC_AHB1RSTR

RAMCFGRST=B_0x0, DMA2DRST=B_0x0, JPEGRST=B_0x0, GPU2DRST=B_0x0, TSCRST=B_0x0, GPDMA1RST=B_0x0, GFXMMURST=B_0x0, CORDICRST=B_0x0, CRCRST=B_0x0, MDF1RST=B_0x0, FMACRST=B_0x0

Description

RCC AHB1 peripheral reset register

Fields

GPDMA1RST	GPDMA1 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the GPDMA1.
CORDICRST	CORDIC reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the CORDIC.
FMACRST	FMAC reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the FMAC.
MDF1RST	MDF1 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the MDF1.
CRCRST	CRC reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the CRC.
JPEGRST	JPEG reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the JPEG.
TSCRST	TSC reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the TSC.
RAMCFGRST	RAMCFG reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the RAMCFG.
DMA2DRST	DMA2D reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the DMA2D.
GFXMMURST	GFXMMU reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the GFXMMU.
GPU2DRST	GPU2D reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the GPU2D.

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