I2C4EN=B_0x0, LPTIM2EN=B_0x0, I2C5EN=B_0x0, UCPD1EN=B_0x0, FDCAN1EN=B_0x0, I2C6EN=B_0x0
RCC APB1 peripheral clock enable register 2
| I2C4EN | I2C4 clock enable This bit is set and cleared by software 0 (B_0x0): I2C4 clock disabled 1 (B_0x1): I2C4 clock enabled |
| LPTIM2EN | LPTIM2 clock enable This bit is set and cleared by software. 0 (B_0x0): LPTIM2 clock disabled 1 (B_0x1): LPTIM2 clock enabled |
| I2C5EN | I2C5 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): I2C5 clock disabled 1 (B_0x1): I2C5 clock enabled |
| I2C6EN | I2C6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): I2C6 clock disabled 1 (B_0x1): I2C6 clock enabled |
| FDCAN1EN | FDCAN1 clock enable This bit is set and cleared by software. 0 (B_0x0): FDCAN1 clock disabled 1 (B_0x1): FDCAN1 clock enabled |
| UCPD1EN | UCPD1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): UCPD1 clock disabled 1 (B_0x1): UCPD1 clock enabled |