I2C4SMEN=B_0x0, I2C5SMEN=B_0x0, LPTIM2SMEN=B_0x0, UCPD1SMEN=B_0x0, I2C6SMEN=B_0x0, FDCAN1SMEN=B_0x0
RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2
| I2C4SMEN | I2C4 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): I2C4 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I2C4 clocks enabled by the clock gating during Sleep and Stop modes |
| LPTIM2SMEN | LPTIM2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): LPTIM2 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): LPTIM2 clocks enabled by the clock gating during Sleep and Stop modes |
| I2C5SMEN | I2C5 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): I2C5 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I2C5 clocks enabled by the clock gating during Sleep and Stop modes |
| I2C6SMEN | I2C6 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): I2C6 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I2C6 clocks enabled by the clock gating during Sleep and Stop modes |
| FDCAN1SMEN | FDCAN1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): FDCAN1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): FDCAN1 clocks enabled by the clock gating during Sleep and Stop modes |
| UCPD1SMEN | UCPD1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): UCPD1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): UCPD1 clocks enabled by the clock gating during Sleep and Stop modes |